1. Field of the Invention
This invention relates generally to semiconductor memory devices such as a flash memory, an EPROM (Erasable and Programmable Read Only Memory) and a ROM (Read Only Memory), and more particularly to a semiconductor memory device of such type that data is read by comparing a data signal from a memory cell with a reference signal/reference voltage from a reference cell.
This application is based on Japanese Patent Application No. Hei 11-291663, the contents of which are incorporated herein by reference.
2. Description of the Related Art
In general, a semiconductor memory device such as a flash memory is constructed so that multi-bit (eight-bit, for example) can be inputted and outputted. A principal structure of a read system in a semiconductor memory device of such type is shown in FIG. 8. As shown in FIG. 8, a memory cell array 1100, comprising non-volatile memory cells (not shown) arranged in a matrix, is divided into blocks 1100-1 to 1100-8 in correspondence with data bits D0 to D7 of external data D, respectively.
A plurality of word lines WL are arranged to extend in the row direction of the memory cell array 100 so as to pass through the blocks 1100-1 to 1100-8 with each word line being connected to control gates of those plural memory cells which belong to the same row. A plurality of bit lines BL are arranged in each block to extend in the column direction with each bit line being connected to one terminals (sources or drains) of current paths of those memory cells which belong to the same column.
The word lines WL of the memory cell array 1100 are connected to a row decoder 1200, while the bit lines BL are connected to a column selector 1300. The column selector 1300 is constructed such that one of the bit lines BL is selected for each of the blocks 1100-1 to 1100-8 in accordance with a column address fed from the outside.
A group of sense amplifiers 1400 comprises eight sense amplifiers of the current detection type corresponding respectively to the block 1100-1 to 1100-8 of the memory cell array 1100 and is constructed so as to detect currents of data signals which will appear on the respective bit lines selected by the column selector 1300. Outputs Vdata-1 to Vdata-8 from the respective sense amplifiers in the sense amplifier group 1400 are supplied to one input parts of differential-type sense amplifiers 1501 to 1508, respectively. The other input parts of these differential-type sense amplifiers 1501 to 1508 are supplied with a reference signal Vref which gives a reference for determining logical values of the data signals as will later be described.
A reference cell 1100R is provided for deriving the reference signal Vref to be supplied to the above-described differential-type sense amplifiers 1501 to 1508 and is constructed comprising a plurality of reference memory cells which correspond in number to those memory cells in one row of the memory cell array 1100. These reference memory cells are connected to a reference bit line BLR. The bit line BLR of the reference cell is connected through a reference column selector 1300R, which is equivalent in terms of load to the column selector 1300, to an input part of a sense amplifier of the current detection type 1400R which corresponds to each sense amplifier in the above-described sense amplifier group 1400.
This sense amplifier 1400R is provided for current-detecting a signal outputted from the reference cell 1100R to thereby supply the above reference signal Vref to the sense amplifiers 1501 to 1508, and is designed such that a level of this reference signal Vref falls in the range between a high level and a low level of a data signal which will be outputted from each sense amplifier in the sense amplifier group 1400 as later described.
A control circuit 1700 is provided for controlling the level of the reference signal Vref in accordance with the mode of operation, For a flash memory, for example, there are provided operation modes such as a write verify mode in which the state of a memory cell into which data has been written is verified and an erase verify mode in which the state of a memory cell for which an erasure of data has been performed is verified. The levels of the reference signal Vref needed in these operation modes are different from each other.
The control circuit 1700 is to adjust the reference cell to a predetermined threshold value in the manufacturing stage of the device. This adjustment to the threshold value is carried out in such a manner that, after the initial erasure of the reference cell, a writing operation thereto is repeated until the threshold value of the reference cell reaches the predetermined threshold value.
More specifically, in order to erase the reference cell a negative voltage of about xe2x88x9216 volts is first applied, for example, to its gate with its source, drain and substrate being applied with a voltage of zero volt to expel electrons from a floating gate in the direction of the substrate in accordance with the FN (Fowler-Nordheim) tunneling method. Thereafter, a positive voltage of about 12 volts is applied, for example, to the gate with the drain being applied with a voltage of about six volts and with the source and substrate being applied with a voltage of zero volt to perform a write operation by injecting electrons into the floating gate in accordance with the CHE (Channel Hot Electron) method.
Thereafter, it is verified whether the correct threshold value has been obtained (write verify) by detecting the current flowing through the reference cell in the condition that a voltage of 3 volts is applied to the gate with the drain and source being applied respectively with voltages of 1 volt and zero volt. If electrons have been injected excessively an erase operation is carried out while a rewrite operation is carried out if electrons lack, depending on the result of the verification. The above process is repeated until the threshold value of the reference cell reaches the predetermined threshold value.
In general, an erase verify and a write verify are carried out with the sensitivity of the sense amplifier 1400R being changed over, More specifically, a load transistor 1401R shown in FIG. 9 (which will later be described) is constructed with a plurality of transistors whose gates and drains are connected in parallel and whose sources are connected to a supply voltage (Vdd) by switching transistors interposed therebetween. By controlling on/off states of the switching transistors, a resistance value of this load transistor and hence the level of the reference signal can be changed.
Although not shown, the above-described control circuit is provided not only for the reference cell but also for the sense amplifiers 1400-1 to 1400-8 one by one to generate various voltages for the read, write, erase and verify operations.
FIG. 9 shows, as an example, a more specific circuit structure of the read system for data D0.
In FIG. 9, the block 1100-1 is that one of the blocks 1100-1 to 1100-8 forming the memory cell array 1100 which comprises the memory cells for storing data corresponding to data D0. This block 1100-1 comprises non-volatile memory cells 1100M-1 arranged in a matrix to which a plurality of word lines WL and a plurality of bit lines BL-1 are connected. A driver 1200D is a driver for driving the word lines WL and constitutes an output stage of the row decoder 1200. The driver 1200D is constructed with CMOS (Complementary Metal Oxide Semiconductor) inverters each having an input part and a source of a p-type transistor which are supplied with a respective one of pre-decoded row address signals.
A selector 1300-1 forms a part of the column selector 1300 shown in FIG. 8, which part serves to select one of the plurality of bit lines BL-1 of the block 1100-1. The selector 1300-1 comprises a plurality of n-type transistors one of which selectively conducts in accordance with pre-decoded column address YS0 to YSn. One end of current paths of these transistors are connected to the bit lines of the block 1100-1, respectively, while the other ends thereof are connected in common to a data line DL-1. With this selector 1300-1, by selectively bringing any one bit of the column address YS0 to YSn to a high level, a corresponding one of the data signals appearing on the plurality of bit lines BL-1 of the block 1100-1 is selectively supplied to the data line DL-1.
A sense amplifier 1400-1 of the current detection type detects a current signal outputted from the memory cell onto the data line DL-1 as a data signal and outputs a voltage signal corresponding to the current signal. This sense amplifier 1400-1 is comprised of a p-type transistor 1401 connected on the power supply side as a load, an n-type transistor 1402 connected between the transistor 1401 and the data line DL-1 for the current detection, and a combination of a p-type transistor 1403 and n-type transistors 1404 and 1405 which constitutes an inverter circuit 1406 for controlling a gate voltage of the transistor 1402. The sense amplifier 1400-1 outputs a voltage signal appearing at a node between the transistor 1401 and the transistor 1402 as a data signal Vdata-1.
The inverter circuit formed by the transistors 1403 to 1405 is constructed such that the level of its output signal can be fixed by a sense amplifier enable signal SAE. Thus, the active state of the sense amplifier 1400-1 is controlled by the sense amplifier enable signal SAE. More specifically, when the sense amplifier enable signal SAE is at a low level, the transistor 1403 functions as a load of the transistor 1404 and the transistor 1405 is fixed in an off state. As a result, an inverter formed by the transistors 1403 and 1404 functions, so that a voltage corresponding to the data signal appearing on the data line DL-1 is outputted to the gate of the transistor 1402 and thus this sense amplifier 1400-1 is brought into an active state.
At this time, if there exists a current flowing through the memory cell, the signal level at the data line DL-1 drops and the inverter receiving this level drives the gate voltage of the transistor 1402 towards a high level. Consequently, the transistor 1402 is turned on, causing the voltage level of the data signal Vdata-1 to be lowered. Conversely, if there exists no current flowing through the memory cell, the gate voltage of the transistor 1402 becomes stable at a level which is a threshold voltage of the transistor higher than the source voltage (the signal level on the data line DL-1) of the transistor 1402. As a result, the transistor 1402 is turned off, so that the voltage level of the data signal Vdata-1 goes up.
When the sense amplifier enable signal SAE is at a high level, the transistor 1405 is fixed in an on state. Consequently, the output signal of the inverter formed by the transistors 1403 and 1404 is brought to a low level, so that the transistor 1402 is fixed in an off state and the data signal Vdata-1 is fixed at a high level. As a result, the sense amplifier 1400-1 becomes inactive.
The reference cell 1100R is constituted comprising a reference memory cell 1100MR whose gate voltage is controlled by a driver 1200DR and a plurality of memory cells 1100MD whose control gates are grounded, all the memory cells 1100MR and 1100MD being connected to the reference bit line BLR. Each of these memory cells 1100MR and 1100MD for the referencing purpose is formed so as to possess properties equivalent to those of a regular memory cell belonging to the above-described memory cell array 1100. The reference memory cell that actually functions is solely the memory cell 1100MR.
The reference bit line BLR is connected to the reference data line DLR through the reference column selector 1300R which is constituted by an n-type transistor whose properties are equivalent to those of a transistor within the column selector 1300. The transistor constituting the column selector 1300R has a gate connected to the power supply and is fixed in the on state. Thus, the bit line BLR is connected through the column selector 1300R and the data line DLR to a sense amplifier 1400R of the current detection type, so that this sense amplifier 1400R always receives a current signal from the reference memory cell 1100MR.
The sense amplifier 1400R of the current detection type has basically the same structure as the above-described sense amplifier 1400-1 of the current detection type and detects the current signal outputted from the reference cell 1100R to the data line DLR to thereby output a voltage signal as the reference signal Vref. More specifically, the sense amplifier 1400R is comprised of a p-type transistor 1401R connected on the power supply side as a load, an n-type transistor 1402R connected between the transistor 1401R and the data line DLR for the current detection, and a combination of a p-type transistor 1403R and n-type transistors 1404R and 1405R which constitutes an inverter circuit 1406R for controlling a gate voltage of the transistor 1402R. The sense amplifier 1400R outputs a voltage signal appearing at a node between the transistor 1401R and the transistor 1402R as the reference signal Vref. The inverter circuit 1406R is controlled by a sense amplifier enable signal SAER, whereby the active state of this sense amplifier is controlled.
The size (e.g., a gate width and a gate length) of each of the transistors 1401 and 1401R is selected such that the current drive capacity of the transistor 1401R within the sense amplifier 1400R is greater than that of the transistor 1401 within the sense amplifier 1400-1. In general, the size of each of the load transistors 1401 and 1401R is determined, taking into consideration the drain current-gate voltage characteristic of the memory cell before data is written thereinto, the drain current-gate voltage characteristic of the memory cell after data was written thereinto and the supply voltage characteristic, in such a manner that the level of the reference signal Vref takes a proper value between the high and low levels of the data signal Vdata-1.
The data signal Vdata-1 from the above-described sense amplifier 1400-1 and the reference signal Vref from the sense amplifier 1400R are supplied to a differential-type sense amplifier 1510 and compared therein. In this example, the differential-type sense amplifier 1501 is adapted to output a signal of logical value xe2x80x9c0xe2x80x9d when the level of the data signal Vdata-1 is higher than that of the reference signal Vref and to output a signal of logical value xe2x80x9c1xe2x80x9d when the level of the data signal Vdata-1 is lower than that of the reference signal Vref.
Although not shown specifically, this semiconductor memory device comprises therein, apart from the constituent elements shown in FIGS. 8 and 9, various other peripheral circuits such as an address buffer for receiving an address from the outside and loading it thereinto as an internal address signal, a pre-decoder for pre-decoding an address, an output buffer for supplying the signals fed from the sense amplifiers to the outside and a control circuit for effecting various controls.
The operation of the conventional semiconductor memory device constructed as described above will now be described with respect to an exemplary case where data (the data corresponding to the external data D0) stored in a memory cell within the block 1100-1 is read out.
The row decoder 1200 drives one of the word lines in the memory cell array 1100 to a high level in accordance with a row address fed from the outside. As a result, all the memory cells connected to the word line driven to the high level are simultaneously activated, so that data signals are outputted in parallel from these memory cells on the one line onto the respective bit lines.
In parallel with this activation of the above memory cells, the column selector 1300-1 selects one of the plural bit lines in the block 1100-1 in accordance with the column address YS0 to YSn, whereby the data signal (a current signal) outputted onto this bit line from the memory cell is supplied through the data line DL-1 to the sense amplifier 1400-1 in the sense amplifier group 1400. This sense amplifier 1400-1 is activated by the sense amplifier enable signal SAE to detect the current signal supplied as the data signal to thereby output the data signal Vdata-1 in the form of a voltage signal to the differential-type sense amplifier 1501.
On the other hand, the reference sense amplifier 1400R is activated, at the same time, by the sense amplifier enable signal SAER to detect the current signal continuously supplied from the reference cell 1100R to thereby output the reference signal Vref in the form of a voltage signal.
As shown in FIG. 10, in response to the sense amplifier enable signal SAE, the data signal Vdata-1 and the reference signal Vref both received by the differential-type sense amplifier 1501 rise simultaneously. Then, the data signal Vdata-1 will become stable at a level which is higher or lower than the reference signal Vref depending upon the data stored in the memory cell whose reading was aimed at. In the example shown in FIG. 10, the memory cell has been erased and is in the condition that data xe2x80x9c1xe2x80x9d is stored. In this case, since the memory cell conducts to flow a current, the data signal Vdata-1 becomes stable at a level lower than the reference signal Vref, so that data xe2x80x9c1xe2x80x9d is read out and supplied to the outside as the data D0.
The sense amplifier 1501 compares the data signal Vdata-1 with the reference signal Vref and outputs a voltage signal having a logical value determined in dependence upon the relation in magnitude between these signals. In this example, since the level of the data signal Vdata-1 is lower than the reference signal Vref, the sense amplifier 1501 outputs a signal with a logical value xe2x80x9c1xe2x80x9d. The output signal of this sense amplifier 1501 is sent as data D0 to the outside through a not-shown output buffer. In parallel with the above-described operation for reading the data D0, reading of data D1 to D7 respectively from the blocks 1100-2 to 1100-8 is carried out.
As shown in FIG. 10, when the sense amplifiers 1400-1 and 1400R are activated simultaneously in response to the activation of the sense amplifier enable signals SAE and SAER, the data signal Vdata-1 and the reference signal Vref simultaneously rise and a voltage difference corresponding to the data develops between these signals, based on which the data is read out.
In the above case, as the source voltage of the transistor 1402 in the sense amplifier 1400-1 shown in FIG. 9 goes up, for example, the output of the inverter circuit 1406 constituted by the transistors 1403 and 1404 goes down, as a result of which the transistor 1402 will be rendered off. However, due to a delay in the inverter circuit 1406, the gate voltage of the transistor 1402 does not follow the change of its source voltage in real time, so that the time when the transistor 1402 goes off will be delayed. As a result, the data signal Vdata-1 goes up to an excessive level and an overshoot of the data signal Vdata-1 is caused. Also, an overshoot of the reference signal Vref is caused for the same reason.
In the above situation, if the reference signal Vref is always generated at a fixed voltage as shown in FIG. 11, the voltage difference between the data signal Vdata-1 and the reference signal Vref momentarily becomes excessively large due to an overshoot of the data signal Vdata-1 caused, so that the differential-type sense amplifier receiving these signals will saturate. Consequently, the operation of this differential-type sense amplifier does not rapidly follow the subsequent change of data, causing a failure in reading the data.
According to the above-described conventional device, however, even if the data signal Vdata-1 overshoots, since the reference signal Vref also overshoots in a similar manner, the relative change of the two signals due to their overshoots is cancelled in substance, so that the required voltage difference can immediately be obtained. Thus, the differential-type sense amplifier does not saturate and the correct reading of data can be achieved.
As described above, in the conventional semiconductor memory device, the reference signal Vref from the reference cell is supplied in common to the plurality of differential-type sense amplifiers so that each differential-type sense amplifier can compare the data signal from a respective one of the blocks with this reference signal to achieve the reading of multi-bit data.
In the meantime, in recent years the storage capacity of this type of semiconductor memory devices has significantly increased and their application has also been diversified. In a recent mobile-phone hand set, for example, it will be required that two processes be simultaneously carried out with a single semiconductor memory device. For example, a list of telephone numbers is read from a non-volatile semiconductor memory device while received data is being stored therein, or received data is erased while the telephone number of a called person is being read and dialed. To meet such requirements, there has been proposed such a structure that a single semiconductor memory device is divided into a plurality of banks to make it possible to simultaneously perform reading from and/or writing into a plurality of memory cells.
As described above, however, the control circuit 1700 is needed for each reference sense amplifier 1400R, and the size of this control circuit 1700 is substantially large even for a single bank. Thus, since the control circuit 1700 has a material influence on the chip area, a semiconductor memory device of the bank structure suffers from a problem that the chip area significantly increases as the number of banks increases.
For a semiconductor memory device of the bank structure, one may conceive, from the viewpoint of simplifying the peripheral circuits, that the circuit for generating the reference signals Vref is shared by the respective banks. In this case, however, the reference signal Vref need to be generated continuously to keep the independency of the operation of each bank. When the reference signal Vref is continuously generated, the difference between the data signal and the reference signal Vref may become momentarily excessively large due to the overshooting of the data signal, which may cause a problem that the reading of data may fail.
It is therefore an object of the present invention to provide a semiconductor memory device which can avoid problems caused by an overshoot of a data signal when reading data, without bringing about an increase of the chip area even when a reference signal, which gives a reference when determining a logical value of a data signal from a memory cell, is constantly generated.
In order to solve the above problems, the present invention has the following structures.
A first semiconductor memory device according to the invention comprises a differential amplifier (for example, a differential-type sense amplifier 150A-0 which will be described later) for comparing a data signal (for example, a data signal VDA-0 which will be described later) from a memory cell (for example, a memory cell 110MA-0 which will be described later) with a reference signal (for example, a reference signal VREF which will be described later) from a reference cell (for example, a reference memory cell 110MR which will be described later) to read data stored in the memory cell, and a circuit (for example, a feedback circuit 200A-0, a signal correction circuit 300A-0, a limiter circuit 400A-0 all of which will be described later) for limiting a relative change between the reference signal and the data signal which are received by the differential amplifier.
With this structure, the data signal from a memory cell will be higher or lower than the reference signal from the reference cell depending on the content of the data. The differential amplifier compares the data signal with the reference signal and outputs a signal representative of the relation in magnitude of these signals. For example, when the data signal is higher than the reference signal, a signal corresponding to data xe2x80x9c1xe2x80x9d is outputted. Conversely, when the data signal is lower than the reference signal, a signal corresponding to data xe2x80x9c0xe2x80x9d is outputted. More specifically, depending upon the content of data stored in a memory cell, the data signal from this memory cell changes with respect to the reference signal, so that a difference will develop between these signals. The differential amplifier amplifies this difference to output a signal corresponding to the data stored in the memory cell.
In the above situation, the relative change between the reference and data signals received by the differential amplifier is limited. In this case, if the relative change between the reference and data signals is limited to such an extent that the reading of data by the amplification of the difference between the data signal from the memory cell and the reference signal is not hampered, the differential amplifier will not excessively be saturated and the output signal of the differential amplifier will quickly follow the variation of the data signal. Therefore, the trouble in reading data due to an overshoot of the data signal can be avoided without causing an increase in chip area and even when the reference signal for giving a reference when determining a logical value of the data signal from the memory cell is constantly generated.
A second semiconductor memory device according to the invention comprises a differential amplifier (for example, a differential-type sense amplifier 150A-0 which will be described later) for comparing a data signal (for example, a data signal VDA-0 which will be described later) from a memory cell (for example, a memory cell 110MA-0 which will be described later) with a reference signal (for example, a reference signal VREF which will be described later) from a reference cell (for example, a reference memory cell 110MR which will be described later) to read data stored in the memory cell, and a circuit (for example, a signal correction circuit 300A-0 which will be described later) for reflecting the data signal upon the reference signal so that a change of the data signal relative to the reference signal is suppressed.
With this structure, the data signal from a memory cell will be higher or lower than the reference signal from the reference cell depending on the content of the data. The differential amplifier compares the data signal with the reference signal and outputs a signal representative of the relation in magnitude of these signals. For example, when the data signal is higher than the reference signal, a signal corresponding to data xe2x80x9c1xe2x80x9d is outputted. Conversely, when the data signal is lower than the reference signal, a signal corresponding to data xe2x80x9c0xe2x80x9d is outputted. More specifically, depending upon the content of data stored in a memory cell, the data signal from this memory cell changes with respect to the reference signal, so that a difference will develop between these signals. The differential amplifier amplifies this difference to output a signal corresponding to the data stored in the memory cell.
In the above situation, the data signal is reflected on the reference signal in such a manner that the change of the data signal from the memory cell relative to the reference signal from the reference cell is suppressed. For example, when the level of the data signal goes up, the level of the reference signal received by the differential amplifier also goes up. Conversely, when the level of the data signal goes down, the level of the reference signal received by the differential amplifier also goes down. As a result, the relative change between the reference and data signals is suppressed, so that the differential amplifier will not excessively be saturated and the output signal of the differential amplifier will quickly follow the variation of the data signal. Therefore, the trouble in reading data due to an overshoot of the data signal can be avoided and data can quickly be read from a memory cell even when the reference signal for giving a reference when determining a logical value of the data signal from the memory cell is constantly generated.
A third semiconductor memory device according to the invention comprises a plurality of banks (for example, banks 100A and 100B which will be described later), and a differential amplifier (for example, a differential-type sense amplifier 150A-0 which will be described later) for comparing a data signal (for example, a data signal VDA-0 which will be described later) from a memory cell (for example, a memory cell 110MA-0 which will be described later) with a reference signal (for example, a reference signal VREF which will be described later) from a reference cell (for example, a reference memory cell 110MR which will be described later) to read data stored in the memory cell in each of the banks, wherein the reference signal is shared by the plurality of banks.
With this structure, the size of the circuit for. generating the reference signal can be minimized by virtue of, among others, the fact that it is not necessary to generate a separate reference signal for each bank and the fact that the number of control circuits for the generation of the reference signal can be reduced. Thus, the chip area (or chip size) can be reduced.
A fourth semiconductor memory device according to the invention comprises a plurality of banks (for example, banks 100A and 100B which will be described later), a differential amplifier (for example, a differential-type sense amplifier 150A-0 which will be described later) for comparing a data signal (for example, a data signal VDA-0 which will be described later) from a memory cell (for example, a memory cell 110MA-0 which will be described later) with a reference signal (for example, a reference signal VREF which will be described later) from a reference cell (for example, a reference memory cell 110MR which will be described later) to read data stored in the memory cell in each of the banks, and a circuit (for example, a feedback circuit 200A-0, a signal correction circuit 300A-0, a limiter circuit 400A-0 all of which will be described later) for limiting a relative change between the reference signal and the data signal which are received by the differential amplifier in each of the banks, wherein the reference signal is shared by the plurality of banks.
With this structure, the data signal from a memory cell will be higher or lower than the reference signal from the reference cell depending on the content of the data. The differential amplifier compares the data signal with the reference signal and outputs a signal representative of the relation in magnitude of these signals. For example, when the data signal is higher than the reference signal, a signal corresponding to data xe2x80x9c1xe2x80x9d is outputted. Conversely, when the data signal is lower than the reference signal, a signal corresponding to data xe2x80x9c0xe2x80x9d is outputted. More specifically, depending upon the content of data stored in a memory cell, the data signal from this memory cell changes with respect to the reference signal, so that a difference will develop between these signals. The differential amplifier amplifies this difference to output a signal corresponding to the data stored in the memory cell.
In the above situation, the relative change between the reference and data signals received by the differential amplifier is limited in each bank. In this case, if the relative change between the reference and data signals is limited to such an extent that the reading of data by the amplification of the difference between the data signal from the memory cell and the reference signal is not hampered, the differential amplifier will not excessively be saturated and the output signal of the differential amplifier will quickly follow the variation of the data signal. Therefore, the trouble in reading data due to an overshoot of the data signal can be avoided in each bank and also data from a memory cell can quickly be read, without causing an increase in chip area, without the need for having the reference signal synchronized with the data signal in each bank and even when the reference signal for giving a reference when determining a logical value of the data signal from the memory cell is continuously generated.
A fifth semiconductor memory device according to the invention comprises a plurality of banks (for example, banks 100A and 100B which will be described later), a differential amplifier (for example, a differential-type sense amplifier 150A-0 which will be described later) for comparing a data signal (for example, a data signal VDA-0 which will be described later) from a memory cell (for example, a memory cell 110MA-0 which will be described later) with a reference signal (for example, a reference signal VREF which will be described later) from a reference cell (for example, a reference memory cell 110MR which will be described later) to read data stored in the memory cell in each of the banks, and a circuit (for example, a signal correction circuit 300A-0 which will be described later) for reflecting the data signal upon the reference signal so that a change of the data signal relative to the reference signal is suppressed in each of the banks, wherein the reference signal is shared by the plurality of banks.
With this structure, the data signal from a memory cell will be higher or lower than the reference signal from the reference cell depending on the content of the data. The differential amplifier compares the data signal with the reference signal and outputs a signal representative of the relation in magnitude of these signals. For example, when the data signal is higher than the reference signal, a signal corresponding to data xe2x80x9c1xe2x80x9d is outputted. Conversely, when the data signal is lower than the reference signal, a signal corresponding to data xe2x80x9c0xe2x80x9d is outputted. More specifically, depending upon the content of data stored in a memory cell, the data signal from this memory cell changes with respect to the reference signal, so that a difference will develop between these signals. The differential amplifier amplifies this difference to output a signal corresponding to the data stored in the memory cell.
In the above situation, the data signal is reflected on the reference signal in each bank in such a manner that the change of the data signal from the memory cell is suppressed relative to the reference signal from the reference cell. For example, when the level of the data signal goes up, the level of the reference signal received by the differential amplifier also goes up. Conversely, when the level of the data signal goes down, the level of the reference signal received by the differential amplifier also goes down. As a result, the relative change between the reference and data signals is suppressed, so that the differential amplifier will not excessively be saturated and the output signal of the differential amplifier will quickly follow the variation of the data signal. Therefore, the trouble in reading data due to an overshoot of the data signal can be avoided in each bank and data can quickly be read from a memory cell, without causing an increase in chip area and even when the reference signal for giving a reference when determining a logical value of the data signal from the memory cell is continuously generated.
The first or fourth semiconductor memory device according to the invention may further comprise a feedback circuit (for example, a feedback circuit 200A-0 which will be described later) for momentarily feeding an output of the differential amplifier back to an input node (for example, an input node NIN which will be described later) thereof, to which the data signal is supplied, when data stored in the memory cell is read.
With this structure, the level of the data signal is corrected in accordance with a difference between the data and reference signals when the output of the differential amplifier is fed back to the input node thereof to which the data signal is supplied. In this case, if an arrangement is made such that the level of the output of the differential amplifier becomes substantially equal to the level of the data signal when the level of the data signal is equal to that of the reference signal, the level of the data signal is rendered substantially equal to that of the reference signal as a result of the feedback of the output of the differential amplifier. That is to say, the relative change between the data and reference signals as received by the differential amplifier is suppressed. Consequently, the differential amplifier will not excessively be saturated and the output signal of the differential amplifier will quickly follow the variation of the data signal. Therefore, data from a memory cell can quickly be read out, without the need for having the reference signal synchronized with the data signal and even when the reference signal is continuously generated.
Each of the first to fifth semiconductor memory devices according to the invention may further comprise a first inverter circuit (for example, an inverter circuit 310A-0 which will be described later) for receiving the data signal from the memory cell to output a first signal (for example, a signal Vsain which will be described later) corresponding to the data signal as one input signal to the differential amplifier, and a second inverter circuit (for example, an inverter circuit 320A-0 which will be described later) for receiving the reference signal from the reference cell and the data signal from the memory cell to output a second signal (for example, a signal Vsaref which will be described later) corresponding to the reference signal as the other input signal to the differential amplifier and for causing the second signal to follow the first signal when the data signal is excessively large.
With this structure, the first inverter circuit receives the data signal from a memory cell and outputs to the differential amplifier the first signal whose level corresponds to the level of the data signal. On the other hand, the second inverter circuit receives the reference signal from the reference cell and outputs to the differential amplifier the second signal whose level corresponds to the level of the reference signal.
When the data signal from a memory cell significantly changes and its level becomes excessive, the first signal outputted from the first inverter circuit changes to a large degree and thus tends to significantly change relatively to the second signal outputted from the second inverter. In this case, the second inverter circuit causes the level of the second signal, which is its output signal, to follow the level of the first signal based on the data signal from the memory cell. As a result, the change of the first signal supplied to the differential amplifier as the data signal is suppressed relatively to the second signal supplied to the differential amplifier as the reference signal, so that the relative change between the reference and data signals supplied to the differential amplifier is limited.
The second inverter circuit may be adapted to shift its input threshold value with respect to the reference signal (for example, a reference signal VREF which will be described later) from the reference cell in accordance with the data signal (for example, a data signal VDA-0 which will be described later) from the memory cell.
With this structure, if the input threshold value to the reference signal is moved toward a lower level when the level of the data signal from the memory cell goes up, the level of the reference signal superficially goes up, and the level of the second signal, which is the output signal, moves in the lower direction. As a result, the second signal follows the first signal and the change of the first signal relative to the second signal is thus suppressed, so that the relative change between the reference and data signals supplied to the differential amplifier is limited. In this manner, the second signal can be caused to follow the first signal when the data signal becomes excessively large.
The first inverter circuit may comprise a first transistor (for example, a p-type transistor 311A-0 which will be described later) of a first conductivity type having a control electrode supplied with the data signal from the memory cell and a current path whose one end is connected to a first power supply and a second transistor (for example, an n-type transistor 313A-0 which will be described later) of a second conductivity type connected as a load between the other end of the current path of the first transistor and a second power supply, while the second inverter circuit may comprise a third transistor (for example, a p-type transistor 321A-0 which will be described later) of the first conductivity type having a control electrode supplied with the reference signal from the reference cell and a current path whose one end is connected to the first power supply, a fourth transistor (a p-type transistor 322A-0 which will be described later) of the first conductivity type having a control electrode supplied with the data signal from the memory cell and a current path whose one end is connected to the other end of the current path of the third transistor and a fifth transistor (for example, an n-type transistor 323A-0 which will be described later) of the second conductivity type connected as a load between the other end of the current path of the fourth transistor and the second power supply, wherein the first inverter circuit outputs a signal appearing between the first transistor and the second transistor (for example, at a drain of a transistor 313A-0 which will be described later) as the. first signal while the second inverter circuit outputs a signal appearing between the fourth transistor and the fifth transistor (for example, at a drain of a transistor 323A-0 which will be described later) as the second signal.
With this structure, if the first conductivity type is a p-type, the second conductivity type an n-type, the first power supply a power supply for applying a positive level and the second power supply a power supply for applying the ground level, the first transistor is rendered off, when the data signal from the memory cell is at a high (H) level, and rendered on when the data signal is at a low (L) level. Therefore, when the data signal is at the high level the ground level from the second power supply is outputted through the second transistor and when the data signal is at the low level the positive level from the first power supply is outputted through the first transistor. That is to say, the first inverter circuit functions as an inverter in which the first signal, which is an output signal thereof, changes in the direction opposite to the direction of change of the data signal from the memory cell, and thus outputs the first signal in accordance with the data signal.
On the other hand, the third transistor provided in the second inverter is rendered off, when the reference signal from the reference cell is at a high level, and rendered on when the reference signal is at a low level. Therefore, when this reference signal is at the high level the ground level from the second power supply is outputted through the fifth transistor as the load, and when the reference signal is at the low level the positive level from the first power supply is outputted through the third transistor. That is to say, the second inverter circuit functions as an inverter in which the second signal, which is an output signal thereof, changes in the direction opposite to the direction of change of the reference signal from the reference cell, and thus outputs the second signal in accordance with the reference signal.
When the data signal from the memory cell changes to an excessively high level, the current flowing through the first transistor is suppressed, so that the level of the first signal drops to a large degree. In this case, the current passing through the fourth transistor, whose control electrode is supplied with the data signal, is suppressed, so that the second signal also drops. Consequently, the second signal follows the first signal, so that the change of the first signal relative to the second signal is suppressed, whereby the relative change between the reference and data signals received by the differential amplifier is limited. Thus, the second signal can be caused to follow the first signal, when the data signal becomes excessively large, by shifting the input threshold with respect to the reference signal from the reference cell in accordance with the data signal from the memory cell.
The first or the fourth semiconductor memory device according to the invention may further comprise a limiter circuit (for example, a limiter circuit 400A-0 which will be described later) for limiting a peak value of the data signal received by the differential amplifier.
With this structure, when the peak value of the data signal supplied to the differential amplifier is limited, the difference between the peak value of the data signal and the reference signal is limited. That is to say, the relative change between the data and reference signals supplied to the differential amplifier is limited. As a result, the differential amplifier will not unduly be saturated and the output signal of the differential amplifier will quickly follow the variation of the data signal. Therefore, data can quickly be read from a memory cell, without the need for having the reference signal synchronized with the data signal and even when the reference signal is continuously generated.
As described above, according to the present invention, by the provision of the arrangement for suppressing/limiting the relative change between the reference signal and the data signal, the difference between the data and reference signals supplied to the differential-type sense amplifier will never be excessively large and, thus, even when this semiconductor memory device is of the bank-structure type the differential-type sense amplifier will not make an incorrect determination of data in each bank, so that the read time in each bank can significantly be shortened.